TARGETS

In order to compile a Spatial application for a particular target, you must follow these general steps:

Compile the Spatial application to generate target-specific code, such as Scala, C++, or Chisel
Compile the target-specific code
(Optional) Export and unpack the compiled code to the target platform
Run the compiled code

1) bin/spatial <app name> <--help or options>
  
2) cd <generated dir> && make

3) x <generated tar>
  
4) bash run.sh <args>

Note that if the generated directory already exists, you will receive a warning. Not deleting the generated directory before step 1 could result in unexpected errors when executing step 2.

Select a target below to see specific instructions for how to compile for that particular device.

+ SCALA SIMULATION

Notes

The Scala backend is a useful tool for debugging at the algorithm level. It has a few advantages and disadvantages, however:

• Advantages:
      o println statements in the Accel will actually print while the app simulates
      o Fastest way to go from source code to execution
• Disadvantages
      o Not cycle accurate.
      o Will not expose pipeline or parallelization bugs
      o Cannot target any devices from generated code.
      o Execution can be slow

Process

      $ # Compile app in Spatial
      $ bin/spatial --sim<br>&nbsp;&nbsp;&nbsp;&nbsp;  $ # Compile backend
      $ cd gen/<app name> && make
      $ # Run app
      $ bash run.sh "<args>"

Note that you can use the input arg -h to see help about the arguments for the app

+ VCS SIMULATION

Notes

VCS is a powerful simulator by Synopsys. The VCS backend is a useful tool for testing the application as it would run on a real FPGA. It has a few advantages and disadvantages, however:

• Advantages:
      o Cycle accurate simulation
      o Debuggable waveforms (see below to learn how to enable logging)
• Disadvantages
      o Requires VCS license.
      o Simulates relatively slowly
      o Does not simulate true interface to peripherals on real FPGAs.

Process

      $ # Compile app in Spatial
      $ bin/spatial <app name> --synth --fpga=VCS <other options>
      $ # Compile backend
      $ cd gen/<app name> && make
      $ # Run app
      $ bash run.sh <args>

Note that you can use the input arg -h to see help about the arguments for the app

If you would like to enable waveform debugging, either with vcd or vpd, edit the file gen/<app name>/vcs.hw-resources/Top-harness.sv and turn either reg vcdon or reg vpdon to 1.

+ AMAZON EC2 F1

Click here for instructions

+ XILINX ZYNQ FAMILY

Notes

To run on this target, you will need a Zynq 7000 board, such as the ZC706 or Zedboard, and a valid license for Vivado for this target. You will also need the appropriate cross-compiler.:

$ sudo apt-get install libc6-armel-cross libc6-dev-armel-cross binutils-arm-linux-gnueabi libncurses5-dev

The generated executable for this target assumes you have a Linux OS installed on the board and have an executable in your path called prog_fpga. To create this executable, download this file and do the following on the Zynq:

      $ mv prog_fpga /usr/bin

      $ chmod +x /usr/bin/prog_fpga

Process

The following process uses the environment variable CLOCK_FREQ_MHZ to configure the clock frequency, or else it uses 125MHz by default.

      $ # Compile app in Spatial
      $ bin/spatial <app name> --synth --fpga= <other options>
      $ # Compile backend
      $ cd gen/<app name> && make # This may take hours
      $ # Transfer to Zynq
      $ scp *.tar.gz <user>@<ip>:
      $  # ssh into Zynq
      $ ssh <user>@<ip>
      $  # Unpack tar.gz and create proper directory structure
      $  tar -xvf <app name>.tar.gz -C <app name> && cd <app name> && mkdir verilog && mv accel.bit.bin verilog
      $ # Run app
      $ sudo ./Top <args>

Note that you can use the input arg -h to see help about the arguments for the app

When you run the program, you will see it print out a line that looks like Design done, ran for 0.003507 ms. This tells you how long the FPGA was active for.

If you want to change the CPU code, you can make edits in gen/<app name>/cpp. The file TopHost.cpp is contains the main() function and uses header files from both the cpp directory and zynq.sw-resources.

+ XILINX Ultrascale MPSoC

Notes

To run on this target, you will need a ZCU102 board or similar and a valid license for Vivado for this target. You will also need the appropriate cross-compiler.:

$ sudo sudo apt-get install g++-aarch64-linux-gnu

The generated executable for this target assumes you have a Linux OS installed on the board. We suggest either building Petalinux with the appropriate FPGA manager drivers, or using the prebuilt image here.
You must also have an executable in your path called prog_fpga. To create this executable, download this file and do the following on the ZCU:

      $ mv prog_fpga /usr/bin

      $ chmod +x /usr/bin/prog_fpga

Process

The following process uses the environment variable CLOCK_FREQ_MHZ to configure the clock frequency, or else it uses 125MHz by default.

      $ # Compile app in Spatial
      $ bin/spatial <app name> --synth --fpga=ZCU <other options>
      $ # Compile backend
      $ cd gen/<app name> && make # This may take hours
      $ # Transfer to Zynq
      $ scp *.tar.gz <user>@<ip>:
      $  # ssh into Zynq
      $ ssh <user>@<ip>
      $  # Unpack tar.gz and create proper directory structure
      $  tar -xvf <app name>.tar.gz -C <app name> && cd <app name> && mkdir verilog && mv accel.bit.bin verilog
      $ # Run app
      $ sudo ./Top <args>

Note that you can use the input arg -h to see help about the arguments for the app

When you run the program, you will see it print out a line that looks like Design done, ran for 0.003507 ms. This tells you how long the FPGA was active for.

+ Altera Arria10 SoC

Notes

To run on this target, you will need an Arria10 board or similar and a valid license for Quartus for this target. You will also need the appropriate cross-compiler.
The generated executable for this target assumes you have a Linux OS installed on the board, and that the core .rbf contains firmware to interact with DRAM.

Process

The following process uses the environment variable CLOCK_FREQ_MHZ to configure the clock frequency, or else it uses 125MHz by default.

      $ # Compile app in Spatial
      $ bin/spatial <app name> --synth --fpga=Arria10 <other options>
      $ # Compile backend
      $ cd gen/<app name> && make # This may take hours
      $ # Transfer to Zynq
      $ scp *.tar.gz <user>@<ip>:
      $  # ssh into Zynq
      $ ssh <user>@<ip>
      $  # Unpack tar.gz and create proper directory structure
      $  # TBA
      $ # Run app
      $ sudo ./Top <args>

Note that you can use the input arg -h to see help about the arguments for the app

When you run the program, you will see it print out a line that looks like Design done, ran for 0.003507 ms. This tells you how long the FPGA was active for.

+ ASIC

Notes

To run on this target, you will need the appropriate Synopsys licenses.
More TBA

Process

The following process uses the environment variable CLOCK_FREQ_MHZ to configure the clock frequency, or else it uses 125MHz by default.

      $ # Compile app in Spatial
      $ bin/spatial <app name> --synth --fpga=ASIC <other options>
      $ # Compile backend
      $ cd gen/<app name> && make # This may take hours
      $ # You should now have reports and generated code for an ASIC, details TBA

+ PLASTICINE

Notes

To run on this target, you will need a Plasticine.
More TBA

Process

      $ # Compile app in Spatial
      $ bin/spatial <app name> <ARGS TBA> <other options>
      $ # Compile backend
      $ cd gen/<app name> && make # This may take hours
      $ # You should now have generated PIR

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